Minotta Zapata, Felipe

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    A weather nowcasting approach as a service for solar energy generation forecast
    (2022-04-05) Minotta Zapata, Felipe; Rodríguez Solís, Rafael A.; College of Engineering; León Colón, Leyda V.; Andrade Rengifo, Fabio; Arzuaga, Emmanuel; Department of Electrical and Computer Engineering; Ríos, Isabel
    This work focuses on the problem of forecasting the energy availability of solar panel arrangements in smart grids. To solve this problem, we propose to use weather radar information to make a 15 minute ahead prediction of the weather conditions in the area where the renewable sources are located. To this end, we propose to use a framework in which the classical approaches, object- and area-based methods, can work in coop fashion to obtain a reliable forecast system. Each weather system is identified and tracked as an object with multiple features. Meanwhile, the movement direction is obtained by a wind vector field generated by the area-based approach. The framework uses the historical information of each system such as average reflectivity and size change to produce an estimated change in both features, as well as the mean movement direction established by the wind vector field to produce a weather forecast. Python was the programming language selected for the implementation which allows portability and integration with different radar applications. Experiments made with TropiNet weather radar network historical data showed similar metric performance as related nowcasting approaches.
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    Methods for scalable levels of parallelism in radix-2 ffts for fpga synthesis
    (2014) Minotta Zapata, Felipe; Jiménez-Cedeño, Manuel; College of Engineering; Ducoudray, Gladys O.; Palomera, Rogelio; Rodriguez, Domingo; Department of Electrical and Computer Engineering; Gonzalez, Ana C.
    The Fast Fourier Transform (FFT) is the main block in many communication systems and signal processing applications, as it allows the fast computation of the discrete Fouier transform (DFT). The DFT, in turn, is used to obtain the spectrum of any finite discrete signal. Hardware implementations of this operation are highly regarded as they provide improved performance with respect to software-based implementations. The purpose of this work was developing a consistent and scalable procedure of generating the address patterns of permutation for any power-of-2 transform size and any folding factor in FFT cores with addressing schemes. Our approach was, mainly, based in 2 memory blocks, an address generator, and radix-2 butteries. The number of butteries determines the level of parallelism. The expected high performance of this FFT core lies in the fact it does not need dedicated permutation hardware between stages. Instead, the data ow is controlled by an address generator. Using this scheme, the impact on consumed resources is significantly mitigated when the number of points of the core is increased. As a result, we obtained a fully scalable FFT core including parallelism level, number of points, and numeric format using this approach.