Irizarry-Valle, Yilda

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An analysis of capacitance multipliers based on general impedance converters
(2009) Irizarry-Valle, Yilda; Palomera-García, Rogelio; College of Engineering; Ducoudray, Gladys O.; Rodríguez-Rodríguez, Domingo; Department of Electrical and Computer Engineering; Cruz, Angel
An analysis at system level applying two port and three terminal network theory is used to establish limitations of frequency and parasitic effects for IC capacitance multipliers. From this analysis, a new model for a floating simulated capacitance based on positive impedance converter was derived. An example of a new electronically tunable implementation based on OTAs and CCCII and focused on low frequency operation has been realized. The circuit was developed with PNP and NPN transistors, whose parameters corresponds to the PRN200P and NR200N of the ALA400 transistor array from AT&T. Pspice simulations show that the circuit can work for ± 2.5 V voltage supplies with a grounded 20 pF capacitor. The equivalent simulated capacitances are in the range of 1 nF to 18 nF. Therefore, a tunable gain factor of 50 to 300 times the capacitance load is achieved in a frequency range of 160 Hz up to 30 kHz.