Contreras Ospino, Boris M.

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    Development of an analytical trapezoidal MOSFET model: Used in a methodology for gate enclosed MOS transistors design based on technology layout rules
    (2020-12-07) Contreras Ospino, Boris M.; Ducoudray Acevedo, Gladys O.; College of Engineering; Serrano Rivera, Guillermo J.; Sallese, Jean M.; Toledo Quiñones, Manuel; Palomera García, Rogelio; Department of Electrical and Computer Engineering; Cáceres Duque, Luis F.
    Gate enclosed or annular MOS transistors are one of the more successful solutions to improve the radiation resistance in an electronic circuit. There are many types of research and works regarding one of the main issues that come from using this type of device and its geometrical shape. Analytical or experimental methods reported different solutions to calculate the reciprocal aspect ratio of annular MOSFETs. Analytical approaches found in the literature use the drawn layout of the gate enclosed MOS transistor. Drawn shapes (rectangular or with broken corners) were deconstructed into smaller devices, such as trapezoid, squares, rectangles, or transformed using dedicated software. Analytical solutions give the designer the advantage of being able to simulate their designs before fabrication. On the post-fabrication stage, a comparison is made between the simulated electrical response of the calculated equivalent aspect ratio and the experimental measurements to ensure the accuracy of the analytical solutions. Transistor parameters such as width and length are among those a designer can modify. This thesis presents an analytical method using a trapezoidal shape for gate enclosed MOSFET width over length calculation. The analytical approach is a relevant part of the methodology for annular MOS transistors design based on technology layout rules, which gives designers a more familiar solution to integrate annular transistors in their circuits.
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    Spice model improvement for annular MOSFET simulation using automated parameter extraction
    (2016-12) Contreras Ospino, Boris M.; Ducoudray Acevedo, Gladys O.; College of Engineering; Palomera García, Rogelio; Serrano Rivera, Guillermo J.; Department of Electrical and Computer Engineering; Cabrera Ríos, Mauricio
    In industry, the creation of an accurate standard MOSFET model in a new technology may take several months. After the model is developed, it can be use to predict the behavior of devices created under the same process, allowing the simulation of a circuit while the final device or prototype is being fabricated. For annular MOSFETs, standard transistor models fail to predict and simulate its electrical behavior, due to its asymmetrical geometry. A validated experimental solution to extract parameters such as MOS technology aspect ratio, can be used for long periods of time. For this reason gaps between old and new solutions for experimental extractions can be found, including used methods and equipments. This thesis presents the design of low-cost hardware and software automated solution to improve a SPICE model for annular/gate enclosed MOSFETs simulation. The automated solution involves the experimental aspect ratio (W/L) extraction of annular MOSFETs, along with DC level 1 parameter calculations. This works also presents a mathematical alternative to calculate the annular transistors aspect ratio through conformal mapping.The accuracy of each extracted parameter and annular MOSFETs W/L were verified by comparing with foundry provided values and other previously validated methods respectively. The results show that the automated implementation for DC level 1 parameter and annular MOSFETs W/L extraction can be use to minimize the user intervention and time for the tests execution.