Rodríguez Latorre, José A.

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    Design of an automated wafer-level parametric test for measuring the reverse recovery parameters of ldmos devices
    (2011) Rodríguez Latorre, José A.; Jiménez Cedeño, Manuel; College of Engineering; Ducoudray, Gladys O.; Palomera García, Rogelio; Department of Electrical and Computer Engineering; Gutierrez, Gustavo
    This thesis presents the development of an automated solution for the measure- ment of reverse recovery parameters (RRPs) of LDMOS devices at the wafer-level. The test circuit developed is based on the topology specified by the JESD24-10 stan- dard. The challenges encountered in the design of this wafer-level parametric test are presented and addressed accordingly. Among these challenges are the appropri- ate component selection, reduction of parasitic inductance along the critical current path, ensuring signal integrity and appropriate test execution. Additionally, the de- sign of the software created for use in test automation is discussed, along with a generalized method for extracting the RRPs from the waveform data. This software was used to execute the reverse recovery test, collect the data and extract the RRPs for similar devices at both package and wafer level. The results show the test circuit was capable of achieving forward bias currents of up to 15A and ∂I/∂t’s of up to 173A/μs. Moreover, the characterization of the test circuit shows that RRPs were precise to within 10%. Lastly, a comparative analysis was performed between pack- age and wafer level measurements. The analysis highlights the differences between package-level and wafer-level measurements.