Polo-Zabaleta, Agenor

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    Design methodology for resource efficient implementation of fast fourier transform cores on field programmable gate arrays
    (2012) Polo-Zabaleta, Agenor; Jiménez-Cedeño, Manuel; College of Engineering; Santiago, Nayda; Rodríguez, Domingo; Department of Electrical and Computer Engineering; Vásquez, Mauricio
    This thesis presents an efficient methodology for the hardware implementation of the Pease Fast Fourier Transform (FFT) radix-2 algorithm, in which, structural regularity from the Kronecker formulation is exploited to perform vertical folding of the transform. An address generator approach is proposed for both, data permutation and phase factor scheduling throughout the stages. The steps required for mapping the methodology onto hardware are explained. The scalability of the core structure is demonstrated by being able to scale the transform size and also by offering the possibility to scale in performance using 2 or 4 processing elements simultaneously. A particular implementation on an FPGA is described analysing its resource consumption and computation speed perspectives. A comparison is provided taking as reference the commercial radix-2 burst I/O FFT core from the FPGA manufacturer Xilinx. When a single processing element is used, an improvement of up to 42% is achieved in logic resource consumption (slices) and up to 29% in the computa- tion performance aspect. When 4 processing elements are used, the performance improvement is up to 81%. A conclusion chapter is provided, remarking the main contributions and possible future directions of this work.