Montaño-Martïnez, Víctor B.

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Design and analysis of scalable floating point fast fourier transforms on field programmable gate arrays
(2009) Montaño-Martïnez, Víctor B.; Jiménez-Cedeño, Manuel; College of Engineering; Rodríguez, Domingo; Arce, Rafael; Department of Electrical and Computer Engineering; Ortiz-Albino, Reyes M.
This project analyzed the impact on the performance of a floating point Fast Fourier Transform (FFT) of modifying design parameters that included the number of points, precision, and folding factor. The performance parameters observed included the latency, resource consumption, maximum clock frequency, and through- put. In order to complete this study, a scalable core of a floating point FFT was designed using a Hardware Description Language (HDL) and implemented on a Xilinx Virtex IV Field Programmable Gate Array (FPGA). The FFT design was structured to allow for scaling the number of points, the number of bits in operands, the folding factor, and the transform direction, either forward or reverse. The behavior of the latency and throughput could be predicted with a set of empirical formulas derived from the design. The resources consumed and maximum frequency provided a good understanding of the effects caused by each generic parameter on the design performance.