Desarden Carrero, Edgardo

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Comprehensive modeling and analysis of power hardware-in-the-loop standard unintentional islanding tests for power inverters
(2024-05-10) Desarden Carrero, Edgardo; Aponte Bezares, Erick; College of Engineering; Ortiz Rivera, Eduardo I.; Darbali Zamora, Rachid; Andrade Rengifo, Fabio; Department of Electrical and Computer Engineering; Román Pérez, Rosa I.
The increase in distributed energy resources (DERs) and rigorous IEEE 1547 ride-through requirements have raised concerns about inverter-based DERs’ ability to detect and mitigate unintentional islanding (UI) incidents while supporting the grid under voltage and frequency abnormalities. The traditional UI test uses a physical RLC load bank, while a recently added Power Hardware in the Loop (PHIL) method offers a faster approach. However, the literature on implementing and validating UI tests using PHIL per IEEE P1547 standards is limited. The interaction of many dynamics within the PHIL testbed introduces uncertainties leading to errors and issues when evaluating UI tests for power inverters with grid support functions (GSFs). In this work, a comprehensive stability and accuracy assessment of the ideal transformer method (ITM) within the PHIL testbed and detailed Simulink and ODE models provide valuable insights into the system performance and dynamics. Experimental results indicate parallelism in behavior across the models, confirming the PHIL testbed's efficacy.