An analysis of capacitance multipliers based on general impedance converters

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Irizarry-Valle, Yilda
Embargoed Until
Palomera-García, Rogelio
College of Engineering
Department of Electrical and Computer Engineering
Degree Level
An analysis at system level applying two port and three terminal network theory is used to establish limitations of frequency and parasitic effects for IC capacitance multipliers. From this analysis, a new model for a floating simulated capacitance based on positive impedance converter was derived. An example of a new electronically tunable implementation based on OTAs and CCCII and focused on low frequency operation has been realized. The circuit was developed with PNP and NPN transistors, whose parameters corresponds to the PRN200P and NR200N of the ALA400 transistor array from AT&T. Pspice simulations show that the circuit can work for ± 2.5 V voltage supplies with a grounded 20 pF capacitor. The equivalent simulated capacitances are in the range of 1 nF to 18 nF. Therefore, a tunable gain factor of 50 to 300 times the capacitance load is achieved in a frequency range of 160 Hz up to 30 kHz.

Un análisis de multiplicadores de capacitancia a nivel de sistemas utilizando teoría de redes de dos puertos y tres terminales permite establecer limitaciones de frecuencia y las debidas a efectos parasíticos. Se presenta un nuevo modelo basado en convertidores positivos de impedancia para simular capacitancias flotantes, y se implementó usando OTAs y CCCII. El circuito fue desarrollado con transistores BJT, modelos PRN200P y NR200N del arreglo de transistores de ALA400 de AT&T. Los resultados obtenidos mediante el software de Cadence Pspice muestran que el circuito opera a un voltaje de ± 2.5 V con una capacitancia de carga de 20 pF. Más aun, las capacitancias equivalentes obtenidas están en un rango de 1 nF hasta 18 nF. Por lo tanto, se logro ́ un factor de ganancia ajustable entre 50 a 300 veces la capacitancia de carga, en un rango de frecuencia que va desde 160 Hz hasta 30 kHz.
Irizarry-Valle, Y. (2009). An analysis of capacitance multipliers based on general impedance converters [Thesis]. Retrieved from