Scalable floating point FPGA units for rapid systems prototyping
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Most modern arithmetic processors rely on pipelining techniques to obtain high throughput. Floating-point(FP) operations are often tlme-consuming and depend on pipelining to accelerate their processes. This project reports the development of scalable, FP arithmetic operators with a variable number of pipeline stages. An algorithm for pipelining insertion was developed and used for FF Multiplication, Addition/Subtraction, Division, and Square Root. The use of this algorithm enables operating frequencies up to 175MHz when implemented on a Xilinx Virtex II FPGA. The developed units offer scalability in terms of precision, range, and pipelining granularity. Also new topologies and improvements for supporting units were achieved. Future work includes automation of the pipelining insertion process.