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dc.contributor.advisorJiménez-Cedeño, Manuel
dc.contributor.authorOrtiz-Flores, Irving
dc.description.abstractMost modern arithmetic processors rely on pipelining techniques to obtain high throughput. Floating-point(FP) operations are often tlme-consuming and depend on pipelining to accelerate their processes. This project reports the development of scalable, FP arithmetic operators with a variable number of pipeline stages. An algorithm for pipelining insertion was developed and used for FF Multiplication, Addition/Subtraction, Division, and Square Root. The use of this algorithm enables operating frequencies up to 175MHz when implemented on a Xilinx Virtex II FPGA. The developed units offer scalability in terms of precision, range, and pipelining granularity. Also new topologies and improvements for supporting units were achieved. Future work includes automation of the pipelining insertion process.en_US
dc.description.sponsorshipEconomical and material support receive from Xilinx University Program, the University of Puerto Rico, and the PRECISE program.en_US
dc.subjectModern microprocesorsen_US
dc.subjectFPGA Virtex IIen_US
dc.titleScalable floating point FPGA units for rapid systems prototypingen_US
dc.typeProject Reporten_US
dc.rights.licenseAll rights reserveden_US
dc.rights.holder(c) 2003 Irvin Ortiz Floresen_US
dc.contributor.committeePalomera, Rogelio
dc.contributor.committeeRodríguez, Domingo
dc.contributor.representativeBollman, Dorothy Engineeringen_US
dc.contributor.collegeCollege of Engineeringen_US
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US

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    Items included under this collection are theses, dissertations, and project reports submitted as a requirement for completing a graduate degree at UPR-Mayagüez.

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