Show simple item record

dc.contributor.advisorJiménez-Cedeño, Manuel
dc.contributor.authorRivera-Ramos, Angel R
dc.date.accessioned2019-05-15T17:59:28Z
dc.date.available2019-05-15T17:59:28Z
dc.date.issued2010
dc.identifier.urihttps://hdl.handle.net/20.500.11801/2318
dc.description.abstractTechnology trends in Power Electronics (PE) design continue to move toward board size reduction and increasing operating frequencies. However, as board sizes are reduced and operating frequencies increased, Electromagnetic Interference (EMI) increasingly becomes a real limiting issue. The inherent parasitic resistance, capac- itance, and inductance present in PE Printed Circuit Board (PCB) traces has been identified as one of the main causes of EMI. As a result, PCB parasitics need to be estimated and minimized. This work presents the development of a fast and accurate PCB parasitic estimation tool, applicable to Power Electronics circuits. This tool uses a semi-lumped approach that divides each PCB trace into simpler segments where analytical equations can be directly applied to obtain the desired parasitic elements. The total parasitic estimate in a trace is computed from the contributions of all its sub-segments and their interactions. The speed advantage gained by this method created the opportunity of using it into automated PCB layout parasitic minimization methods.en_US
dc.description.abstractLas tecnologías de diseño en electrónica de potencia continuan avanzado en la dirección de producir circuitos cada vez más pequeños y capaces de operar a frecuencias más altas. Sin embargo, a medida que cumplimos con los requisitos de diseño previamente mencionados, la Interferencia Electromagnética se convierte en una gran limitante. Una de las principales causas de Interferencia Electromagnética es la prescencia de componentes resistivos, inductivos y capacitivos, lamados comúnmente parasíticos. Para solucionar este problema es necesario estimar los parasíticos presentes en un circuito impreso para entonces aplicar estrategias con el, destinadas a reducirlos al mínimo. Con este objetivo en mente, presentamos el desarrollo de una herramienta de estimación de parasíticos, aplicada a circuitos de electrónica de potencia. Esta herramienta divide cada trazo de un circuito impreso en segmentos más simples, a los cuales se le aplica ecuaciones analíticas para hallar los parasíticos presentes en los mismos. El estimado total de parasíticos en un trazo es calculado mediante la contribución individual de sus segmentos e interacciones. La rapidez computacional alcanzada en el método crea la oportunidad de utilizar el mismo en métodos automáticos de minimización de parasíticos.en_US
dc.description.sponsorshipERC program of the national science foundation under the award number EEC-9731667.en_US
dc.language.isoEnglishen_US
dc.titleAnalytical model development for lc parasitic estimation in power electronics circuitsen_US
dc.typeProject Reporten_US
dc.rights.licenseAll rights reserveden_US
dc.rights.holder(c) 2010 Angel R Rivera-Ramosen_US
dc.contributor.committeePalomera-Garcia, Rogelio
dc.contributor.committeeVélez, Miguel
dc.contributor.representativePortnoy, Arturo
thesis.degree.levelM.E.en_US
thesis.degree.disciplineElectrical Engineeringen_US
dc.contributor.collegeCollege of Engineeringen_US
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.description.graduationSemesterSpring (2nd Semester)en_US
dc.description.graduationYear2010en_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

  • Theses & Dissertations
    Items included under this collection are theses, dissertations, and project reports submitted as a requirement for completing a graduate degree at UPR-Mayagüez.

Show simple item record

All rights reserved
Except where otherwise noted, this item's license is described as All Rights Reserved