Publication:
An analysis of capacitance multipliers based on general impedance converters

dc.contributor.advisor Palomera-García, Rogelio
dc.contributor.author Irizarry-Valle, Yilda
dc.contributor.college College of Engineering en_US
dc.contributor.committee Ducoudray, Gladys O.
dc.contributor.committee Rodríguez-Rodríguez, Domingo
dc.contributor.department Department of Electrical and Computer Engineering en_US
dc.contributor.representative Cruz, Angel
dc.date.accessioned 2019-05-15T17:59:29Z
dc.date.available 2019-05-15T17:59:29Z
dc.date.issued 2009
dc.description.abstract An analysis at system level applying two port and three terminal network theory is used to establish limitations of frequency and parasitic effects for IC capacitance multipliers. From this analysis, a new model for a floating simulated capacitance based on positive impedance converter was derived. An example of a new electronically tunable implementation based on OTAs and CCCII and focused on low frequency operation has been realized. The circuit was developed with PNP and NPN transistors, whose parameters corresponds to the PRN200P and NR200N of the ALA400 transistor array from AT&T. Pspice simulations show that the circuit can work for ± 2.5 V voltage supplies with a grounded 20 pF capacitor. The equivalent simulated capacitances are in the range of 1 nF to 18 nF. Therefore, a tunable gain factor of 50 to 300 times the capacitance load is achieved in a frequency range of 160 Hz up to 30 kHz. en_US
dc.description.abstract Un análisis de multiplicadores de capacitancia a nivel de sistemas utilizando teoría de redes de dos puertos y tres terminales permite establecer limitaciones de frecuencia y las debidas a efectos parasíticos. Se presenta un nuevo modelo basado en convertidores positivos de impedancia para simular capacitancias flotantes, y se implementó usando OTAs y CCCII. El circuito fue desarrollado con transistores BJT, modelos PRN200P y NR200N del arreglo de transistores de ALA400 de AT&T. Los resultados obtenidos mediante el software de Cadence Pspice muestran que el circuito opera a un voltaje de ± 2.5 V con una capacitancia de carga de 20 pF. Más aun, las capacitancias equivalentes obtenidas están en un rango de 1 nF hasta 18 nF. Por lo tanto, se logro ́ un factor de ganancia ajustable entre 50 a 300 veces la capacitancia de carga, en un rango de frecuencia que va desde 160 Hz hasta 30 kHz. en_US
dc.description.graduationYear 2009 en_US
dc.identifier.uri https://hdl.handle.net/20.500.11801/2332
dc.language.iso English en_US
dc.rights.holder (c) 2009 Yilda Irizarry-Valle en_US
dc.rights.license All rights reserved en_US
dc.title An analysis of capacitance multipliers based on general impedance converters en_US
dc.type Thesis en_US
dspace.entity.type Publication
thesis.degree.discipline Electrical Engineering en_US
thesis.degree.level M.S. en_US
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